IP Modeling and Reuse for SoC Design Using Standard Bus
نویسنده
چکیده
Most of system on chip (SoC) being designed today could reach several millions of gates and more than 2 GHz operating frequency. In order to implement such system, designers are increasingly relying on reuse of intellectual property (IP). In order to effectively re-use an IP in a system chip, a set of abstracted models of the IP must be provided that enable the complete design and verification of the system chip that instantiates the IP. This work addresses the main issues in SoC design, namely the system design methodology, system level modelling, and IP integration for platform based design. The methodology presented allows the reuse and the integration of IP components at any level of the design process, using IP modelling methodology. At each stage, the system functionality and its characteristics can be evaluated and validated. In this way, IP modelling presents a number of unique technical challenges. This paper discusses these challenges and offers a new methodology approach for IP modelling during system level design flow.
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تاریخ انتشار 2007